BeBox History
Be Newsletter #52 Extract
Issue 52, December 4, 1996
By Jean-Louis Gassée
. . .
When we moved from the AT&T Hobbit processor to the PowerPC, the 604 was
unavailable and projected to be prohibitively expensive (for us at least). The
601 was clearly an ephemeral product. Only the 603 had the future and the price
we liked. There was one glitch, however: Motorola stated that multiprocessor
systems couldn't be implemented with the 603. On closer examination, this
techno-marketing statement was based on the absence of cache-coherency hardware
on the 603. Loosely speaking, cache coherency is a function by which one
processor can advise others of the "pollution" of data contained in its cache,
thus preventing its colleagues from reliance on now-invalid copies of the same
data in their own caches. We decided we could work around that problem, mostly
in software, and we produced working 603-based dual-processor hardware. In most
cases, the workaround we designed imposes an invisible performance penalty.
Now, imagine a situation where two threads, one to each processor, work on the
same data. This can give rise to sizable overhead when the caches have to be
constantly updated. One can construct cases when two processors perform more
slowly than when one BeBox CPU is turned off. Fortunately, in real life, the
system performs loosely coupled tasks most of the time, and the 603 penalty
isn't a factor. The 604 is now available, without much of the earlier price
penalty exacted on our small company with its limited purchase power; it
features cache-coherency hardware and thus does away with the limitations of
the 603 in MP applications. If not all, most PowerMac licensees have 604
dual-processor hardware but not much system software to take advantage of it, a
situation we intend to deal with promptly.
. . .
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